Apparatus and method for controlling voltage regulator and power supply apparatus

ABSTRACT

In a method for controlling a voltage regulator, first and second charge storage devices are switchably connected between a voltage source and the voltage regulator. The first storage device is switched into connection with the voltage source until the voltage on it reaches a predetermined level. The first storage device is disconnected from the voltage source and switched into connection with the second storage device and the voltage regulator until the voltage input to the voltage regulator falls below a predetermined level. The above operations are repeated.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an apparatus and method forcontrolling a linear voltage regulator.

[0003] 2. Description of the Related Art

[0004] Linear voltage regulators are well known electronic devices. Theyare used to produce a steady output voltage at a predetermined levelfrom an input voltage which may vary. The input voltage is higher thanthe output voltage and heat is dissipated in the regulator. The powerdissipated given a constant load current is proportional to the voltagedrop between the input and the output. For example, in a batteryoperated system where the operating voltage of the circuitry issignificantly lower than the battery voltage, reducing the powerdissipation in the regulator will lead to improved battery life. It willalso reduce the thermal efficiency requirements of the regulator therebyallowing a small and cheaper package and pass transistor to be used.Conventionally, power supply efficiency has been improved by replacingthe pass transistor with a switched inductor. A buck converter uses suchan arrangement. However, the inductor tends to be a large and expensivecomponent and is generally not suitable for miniaturization.

SUMMARY OF THE INVENTION

[0005] Therefore, an object of the present invention is to provide amethod and circuitry for improving the efficiency of a linear regulatorwithout using ferroelectric components.

[0006] Another object of the present invention is to reduce the inputvoltage to a linear regulator be switching small amounts of changebetween capacitors.

[0007] In an aspect of the present invention, a method for controlling avoltage regulator is achieved by a) providing first and second chargestorage devices switchably connected between a voltage source and thevoltage regulator; by b) switching the first storage device intoconnection with the voltage source until the voltage on it reaches apredetermined level; by c) disconnecting the first storage device fromthe voltage source and switching it into connection with the secondstorage device and the voltage regulator until the voltage input to thevoltage regulator falls below a predetermined level; and by d) repeatingsteps b) and c).

[0008] Here, the storage devices may be capacitors connected in parallelwith the voltage regulator, across the voltage source.

[0009] Also, the switching may be performed by two switches connected inseries, one between the voltage source and the first storage device andthe other between the first and second storage devices.

[0010] Also, the first storage device may be significantly larger thanthe second storage device.

[0011] In another aspect of the present invention, an apparatus forcontrolling a voltage regulator includes a voltage source, and a firstand second charge storage devices connected between the voltage sourceand the voltage regulator. A section connects the first storage deviceto the voltage source and disconnects it from the second storage deviceand the voltage regulator until the voltage on the first storage devicereaches a predetermined level. Another section disconnects the firststorage device from the voltage source and connects it to the secondstorage device and the voltage regulator until the input voltage to thevoltage regulator falls below a predetermined level. Still anothersection switches the storage devices between the 2 modes of operation.

[0012] Here, the storage devices may be capacitors, and the connectingsection may include two switches are connected in series between thevoltage source and the first storage device, the other between the twostorage devices.

[0013] Also, it is preferable that the first storage device issubstantially larger than the second storage device.

[0014] In still another aspect of the present invention, a power supplyapparatus includes a power supply, a voltage regulator, and first andsecond capacitors provided between the power supply and the voltageregulator in parallel to the power supply. The apparatus furtherincludes a first switch provided between the power supply and the firstcapacitor to open or close in response to a first control signal, and asecond switch provided between the power supply and the second capacitorto open or close in response to a second control signal. A controlcircuit generates the first and second control signals to the first andsecond switches such that the second switch opens and then the firstswitch closes when a voltage of the second capacitor decreases to afirst predetermined level, and such that the first switch opens and thesecond switch closes after a first predetermined time period from theclosing the first switch.

[0015] Here, the first predetermined time may be a time period until avoltage of the first capacitor reaches a second predetermined levelafter the first switch is closed.

[0016] Also, the control circuit may generate the first and secondcontrol signals to repeat a switching operation in which the secondswitch opens and then the first switch closes when the voltage of thesecond capacitor decreases to the first predetermined level, and thefirst switch opens and the second switch closes after the firstpredetermined time period from the closing the first switch.

[0017] Also, the control circuit may monitor the voltage of the secondcapacitor and generates the first and second control signals based onthe monitoring result.

[0018] Also, it is preferable that the second capacitor is larger incapacitance than the first capacitor.

[0019] In yet still another aspect of the present invention, a powersupply apparatus includes a power supply, a voltage regulator, and firstand second capacitors provided between the power supply and the voltageregulator in parallel to the power supply. The apparatus furtherincludes a first switch provided between the power supply and the firstcapacitor to open or close in response to a first control signal, and asecond switch provided between the power supply and the second capacitorto open or close in response to a second control signal. A controlcircuit generates the first and second control signals to the first andsecond switches such that the second switch opens and then the firstswitch closes when a voltage of the first capacitor decreases to a firstpredetermined level, and such that the first switch opens and the secondswitch closes after a first predetermined time period from the closingthe first switch.

[0020] Here, the first predetermined time may be a time period until avoltage of the first capacitor reaches a second predetermined levelafter the first switch is closed.

[0021] Also, the control circuit may generate the first and secondcontrol signals to repeat a switching operation in which the secondswitch opens and then the first switch closes when the voltage of thefirst capacitor decreases to the first predetermined level, and thefirst switch opens and the second switch closes after the firstpredetermined time period from the closing the first switch.

[0022] Also, the control circuit may monitor the voltage of the firstcapacitor and generate the first and second control signals when thevoltage of the first capacitor decreases to the first predeterminedlevel.

[0023] Also, it is preferable that the second capacitor is larger incapacitance than the first capacitor.

[0024] Also, the control circuit may monitor the voltage of the firstcapacitor and an output voltage of the voltage regulator and generatethe first and second control signals based on the voltage of the firstcapacitor to the output voltage of the voltage regulator.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] A preferred embodiment of the present invention will now bedescribed in detail by way of example with reference to the accompanyingdrawings in which:

[0026]FIG. 1 is a block diagram of a system embodying the presentinvention;

[0027]FIG. 2 shows the capacitor voltages for various states of thecircuit FIG. 1;

[0028]FIG. 3 shows an implementation of a second embodiment of thecontrol circuitry of FIG. 1; and

[0029]FIG. 4 shows the voltage signal transitions for various points inthe circuit of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] A control apparatus of a linier regulator according to a firstembodiment of the present invention is shown in FIG. 1. The controlapparatus is comprised of a DC power supply or battery 2 which suppliesan input voltage V_(in). The power supply is connected in parallel withtwo capacitors C₁ and C₂. The capacitor C₁ is separated from the voltageV_(in) by a switch S₁. A further switch S₂ separates the capacitors C₁and C₂ A linear regulator 4 is connected across the circuit downstreamof the capacitor C₂ and has an output which produces a voltage V_(out)and a current I_(load).

[0031] A control circuit 6 monitors the input voltage V_(in) to thelinear regulator 4 and in response to the monitoring result, suppliescontrol signals to the switches S₁ and S₂ which can be closed. Theswitch S₁ when closed will enable the capacitor C₁ to charge. The switchS₂ when closed will allow the capacitor C₂ to charge from the capacitorC₁ at the same time as providing input charge to the linear regulator 4.

[0032] The control circuit 6 is responsive to the voltage of the inputto the linear regulator 4. When this voltage falls below a predeterminedlevel, corresponding to the minimum required to maintain the outputvoltage V_(out), the control circuit 6 opens the switch S₂ and closesthe switch S₁, in that order. This causes the capacitor C₁ to be chargedup to the battery voltage, whereupon the switch S₁ is reopened and theswitch S₂ is closed (again in that order). A charge is transferred fromthe battery to the capacitor C₁ in the first stage where the switch S₁is closed and in the second stage when the switch S₁ is opened and theswitch S₂ is closed, the charge is transferred from the capacitor C₁ tothe capacitor C₂ until the voltages across the capacitors are equalized.Subsequently, if a constant load current I^(load) is drawn from theregulator 4, the voltage on the capacitors C₁ and C₂ will decreaselinearly until the switching threshold is reached again. Typically, theswitching threshold will be set to such a level that recharging thecapacitor C₁ by closing the switch S₁ and opening the switch S₂, andswitching back to discharge of the capacitor C₁ by opening the switch S₁and closing the switch S₂ can happen before the input voltage to thelinear regulator 4 falls beneath the minimum required to maintainvoltage V_(out).

[0033] The traces in FIG. 2 show the voltage across the capacitorslinked to the switching cycle, assuming that there are no resistivelosses in the circuit. In practice, there will of course be resistivelosses and the traces will be modified accordingly.

[0034] The average voltage at the input to the regulator 4 is theaverage of V_(C2), and is given by: $\begin{matrix}{V_{ave} = \frac{V_{set} + V_{out} + V_{do}}{2}} & (1)\end{matrix}$

[0035] A voltage V_(set) is determined by considering the energytransferred between the capacitors. The energy stored in the capacitorC₁ while the switch S₁ is closed is given by: $\begin{matrix}{E_{1} = \frac{C_{1} \cdot V_{in}^{2}}{2}} & (2)\end{matrix}$

[0036] The energy remaining in the capacitor C₂ at the moment the switchS₂ closes is given by: $\begin{matrix}{E_{2} = \frac{C_{1} \cdot \left( {V_{out} + V_{do}} \right)^{2}}{2}} & (3)\end{matrix}$

[0037] By conservation of energy, the combined energy of the capacitorsC₁ and C₂ in parallel is given by: $\begin{matrix}{E_{c} = {{E_{1} + E_{2}} = {\frac{C_{1} \cdot V_{in}^{2}}{2} + \frac{C_{2} \cdot \left( {V_{out} + V_{do}} \right)^{2}}{2}}}} & (4)\end{matrix}$

[0038] Also: $\begin{matrix}{E_{c} = \frac{\left( {C_{1} + C_{2}} \right) \cdot V_{set}^{2}}{2}} & (5)\end{matrix}$

[0039] Therefore: $\begin{matrix}{V_{set} = {\sqrt{\frac{2 \cdot E_{c}}{C_{1} + C_{2}}} = \sqrt{\frac{{C_{1} \cdot V_{in}^{2}} + {C_{2}\left( {V_{out} + V_{do}} \right)}^{2}}{C_{1} + C_{2}}}}} & (6)\end{matrix}$

[0040] From the above equations, it can be deducted that the power drawnfrom the battery 2 is given by: $\begin{matrix}{P = {{I_{load} \cdot V_{set}} = {\frac{I_{load}}{2}.\left\lbrack {\sqrt{\frac{{C_{1} \cdot V_{in}^{2}} + {C_{2}\left( {V_{out} + V_{do}} \right)}^{2}}{C_{1} + C_{2}}} + V_{out} + V_{do}} \right\rbrack}}} & (7)\end{matrix}$

[0041] The power drawn from the battery 2 without the switch/capacitorcircuit is given by:

P _(old) =I _(load) ·V _(in)  (8)

[0042] Therefore, the improvement in power efficiency given by thecircuit (ignoring power lost during the switching due to gatecapacitance and switch/capacitor series resistance) is: $\begin{matrix}{\frac{P}{P_{old}} = {\frac{1}{2 \cdot V_{in}} \cdot \left\lbrack {\sqrt{\frac{{C_{1} \cdot V_{in}^{2}} + {C_{2}\left( {V_{out} + V_{do}} \right)}^{2}}{C_{1} + C_{2}}} + V_{out} + V_{do}} \right\rbrack}} & (9)\end{matrix}$

[0043] It can be seen by examination of equation (1) that the bestefficiency is obtained when C₂>>C₁ such that V_(set=>(V) _(out)+V_(do)).Then the improvement in efficiency approaches the ratio: $\begin{matrix}{\frac{P}{P_{old}} = \frac{V_{out} + V_{do}}{V_{in}}} & (10)\end{matrix}$

[0044] The period T between successive activations of the switches isdependent on the load current: $\begin{matrix}{T = \frac{\left\lbrack {V_{set} - \left( {V_{out} + V_{do}} \right)} \right\rbrack \cdot \left( {C_{1} + C_{2}} \right)}{I_{load}}} & (11)\end{matrix}$

[0045] or substituting for V_(set). $\begin{matrix}{T = {\frac{\left( {C_{1} + C_{2}} \right)}{I_{load}}\left\lbrack {\sqrt{\frac{{C_{1} \cdot V_{in}^{2}} + {C_{2}\left( {V_{out} + V_{do}} \right)}^{2}}{C_{1} + C_{2}}} - \left( {V_{out} + V_{do}} \right)} \right\rbrack}} & (12)\end{matrix}$

[0046] So the switching period is inversely proportional to the loadcurrent, as would be expected. The period can be increased (to savepower lost in switching) by making the capacitor C₁ as large aspossible.

[0047]FIG. 3 shows the control apparatus of the regulator according tothe second embodiment of the present invention. The portion of thecircuit corresponding to the control circuit 6 of FIG. 1 is 20 shown indotted outline. The switches S₁ and S₂ are P-channel FET devices. Thefeedback arrangement of the voltage which in FIG. 1 is from the inputvoltage to the linear regulator (given by the voltage on the capacitorC₂) is in the embodiment replaced by feedback from the voltage on thecapacitor C₁ and from the voltage output of the regulator 4 for V_(out).The output voltage V_(out) is the voltage input to a voltage divider R₁and R₂ and the output of this divider is provided to one input of acomparator 8. The voltage on the capacitor C₁ is fed by a furthervoltage divider R₃ and R₄ to the other inverted input of a comparator 8.The comparator has a hysteresis characteristic and outputs a pulse witha predetermined duration time when the output of the voltage divider R₃and R₄ is lower than that of the voltage divider R₁ and R₂. The pulseduration time is sufficient to charge the capacitor C₁ to the powersupply voltage.

[0048] The output of the comparator 8 is provided to the two inputs of aflip-flop comprising a pair of NAND gates and a pair of AND gates. Theoutput of the comparator 8 goes directly to the input of a first NANDgate 10 and by the inverter 12 to the second NAND gate 14. The output ofthe second NAND gate 14 is connected to the other input of the firstNAND gate 10, and the output of the first NAND gate 10 is connected tothe second input of the second NAND gate 14. The output of the firstNAND gate 10 is also connected to an input of an AND gate 16 whilst theoutput of the second NAND gate 14 is connected to an input of an ANDgate 18. The other input of each of these AND gates 16 and 18 isconnected to a start/enable line. The purpose of the AND gates is toenable the regulator 4 to start up.

[0049]FIG. 4 shows the voltage at various points in the circuit duringstart up and subsequent operation following the application of a signalto the start/enable line.

[0050] When the start/enable signal is low (probably by default when thebattery 2 power V_(bat) is applied) as shown in FIG. 4A, both FETswitches S₁ and S₂ are forced on, and the battery 2 voltage is applieddirectly to the regulator 4 input. This enables the regulator 4 to startup as normal in a low efficiency mode. This mode may also be used if thebattery voltage falls to the point where the control apparatus ceases toprovide any efficiency improvement or, alternatively, may be used insituations where harmonic interference caused by switching isundesirable (e.g., in a radio subsystem).

[0051] When the start/enable signal is set high as shown in FIG. 4A,e.g., by a micro-controller I/O port, the voltage on the capacitor Clwill be higher than output of the regulator 4 and the output of thecomparator 8 will be low as shown in FIG. 4B. Therefore, the voltageV_(gs1) (the S₁ enabling voltage) will be high as shown in FIG. 4D, andso the switch S₁ will be open, and the voltage V_(gs2) (S₂ enablingvoltage) will be low as shown in FIG. 4E, which means the switch S₂ willbe closed. If a load current is drawn from the regulator 4, the voltageon the capacitors C₁ and C₂ will fall as shown in FIGS. 4F and 4G. Whenthe voltage V_(C1) reaches a predetermined switching point,V_(threshold) (V_(thr) in FIG. 4), the comparator 8 output will go highas shown in FIG. 4B. The switching point is set relative to the outputvoltage V_(out) of the regulator 4, and can be adjusted by varying theratio of R₃ to R₄. It should be chosen such that the voltage across theregulator 4 remains larger than the maximum dropout voltage V_(do) (thevoltage drop across the regulator 4) at all times and under all loadcurrent conditions. Clearly, allowance needs to be made for the timetaken to recharge the capacitor C₁, considering that in a practicalimplementation there will be a finite switching time for the FET's, andseries resistance means that the capacitors do not chargeinstantaneously.

[0052] When the comparator 8 output switches to high in response to areduction in the capacitor voltage V_(c1) or the output voltage V_(out),the flip-flop will cause the voltage V_(gs2) to go high as shown in FIG.4E. Thereby, the switch S₂ is opened. Also, the flip-flop will cause thevoltage V_(gs1) to go low as shown in FIG. 4D, thereby closing theswitch S₁. The capacitor C₁ will then be charged and the voltage V_(c1)will increase as shown in FIG. 4F. This will cause the comparator 8output to go low as shown in FIG. 4B when the voltage V_(c1) reaches apredetermined level. At this time, the switch S₁ is opened again asshown in FIG. 4D and the switch S₂ is closed as shown in FIG. 4E. Then,the cycle begins again.

[0053] The small amount of resistance in the switching circuit which wasmentioned above consists of the series resistance of the battery, orvoltage source, the series resistance of the switches andinterconnections, and the series resistance of the capacitors. Theeffect of this is twofold. Firstly, it will reduce the efficiency of thecircuit due to energy dissipation. Secondly, it will introduce a delayof the transfer of charge between the battery 2 and the capacitors C₁and C₂. Any inductance in the circuit will also add to this delay. Thismeans that the “on” time of the switch S₁ must be increased to allow thecapacitor C₁ to be fully charged.

[0054] The circuit shown in FIG. 3 relies on propagation delays throughthe feedback circuitry to provide this delay. A more deterministicmethod might include a hysteresis component in the comparator, such thatthe voltage on C₁ has to approach the battery voltage before thecomparator switches back.

[0055] A second consideration is the time required to turn thetransistor on and off. This is determined by the size of the transistor,the gate capacitance, and the drive capability of the AND gates.Clearly, if there is a period during which both transistors are switchedon, the capacitor C₂ will be directly charged from the battery 2, andthe voltage of the regulator 4 input will be consequently higher. Thisleads to a reduction in efficiency of the circuit which can be dramatic.The NAND/inverter circuit is used to prevent any overlap betweenswitching off one transistor and switching on the other. Nevertheless,this relies on the propagation delay through the NAND gates beinggreater than the switching time of the transistors FET1 and FET2. Thedelay can be increased by inserting extra delay buffers in the feedbackpath between the output of one NAND gate and the input of the other.

[0056] Another effect of the transistor switching time increases losswhilst the transistors are partially on and, hence resistive. Ideally,vary fast transistors should be used. However, this can usually only beachieved at the expense of series resistance and/or maximum currentcapability. Therefore, a compromise must be made based on the loadrequirements. Furthermore, it should be noted that the peak current flowfrom the battery I_(peak) can be high if the switch S₁ switches veryquickly. A slower turn on time may be desirable to limit the transientcurrent and possible associated noise problems.

[0057] The most obvious practical consideration is in the selection ofthe capacitors. Clearly, low ESR dielectrics such as ceramics willcontribute less to the overall loss in the switching system. However,the larger the value of the capacitor C₁ becomes, the lower theswitching frequency becomes, (furthermore, the capacitor C₂ should besignificantly larger than the capacitor C₁) and this will increaseefficiency. This is because a significant amount of power is lost in theswitching of the gates and the transistors and therefore a low switchingfrequency is desirable. Preferably, therefore, the capacitor C₂ shouldbe chosen to be as large as possible within the space and costlimitations of the system.

[0058] The switching transistors and feedback circuit could beintegrated into a BiCMOS process with the linear regulator Bipolar/CMOS(CMOS: Complementary Metal Oxide Semiconductor). This would mean thatthe only external components required would be the capacitors. Alllinear regulators do in fact require an input and an output capacitorfor stability and smoothing and, therefore, in fact only one extracapacitor C₁ would be required. The system therefore offers considerableefficiency gains over a standard linear regulator through the additionof one extra capacitor. The system also offers advantages overferro-electric switch mode converters such as buck regulators.Capacitors are generally cheaper, smaller, have lower series resistanceand radiate less than inductors and transformers. All of these arequalities which are of particular importance for portabletelecommunications systems.

[0059] Where higher current applications are required, it is necessaryto use tantalum or electrolytic capacitors. Large transistors are alsorequired for low resistance in high current applications.

[0060] Interference due to high peak charge currents may occur, and theswitching frequency is not predictable, this being dependent on the loadcurrent. This can easily be overcome by using a fixed frequency clock,rather than a comparator to drive the switches. This arrangement,however, would be less efficient at low loads.

What is claimed is:
 1. A method for controlling a voltage regulatorcomprising the steps of: a) providing first and second charge storagedevices switchably connected between a voltage source and the voltageregulator; b) switching the first storage device into connection withthe voltage source until the voltage on it reaches a predeterminedlevel; c) disconnecting the first storage device from the voltage sourceand switching it into connection with the second storage device and thevoltage regulator until the voltage input to the voltage regulator fallsbelow a predetermined level; and d) repeating steps b) and c).
 2. Themethod according to claim 1, wherein the storage devices comprisecapacitors connected in parallel with the voltage regulator, across thevoltage source.
 3. The method according to claim 1, wherein theswitching is performed by two switches connected in series, one betweenthe voltage source and the first storage device and the other betweenthe first and second storage devices.
 4. The method according to claim1, wherein the first storage device is significantly larger than thesecond storage device.
 5. An apparatus for controlling a voltageregulator comprising: a voltage source; a first and second chargestorage devices connected between the voltage source and the voltageregulator; means for connecting the first storage device to the voltagesource and disconnecting it from the second storage device and thevoltage regulator until the voltage on the first storage device reachesa predetermined level; means for disconnecting the first storage devicefrom the voltage source and connecting it to the second storage deviceand the voltage regulator until the input voltage to the voltageregulator falls below a predetermined level; and means for switching thestorage devices between the 2 modes of operation.
 6. The apparatusaccording to claim 5, wherein the storage devices are capacitors.
 7. Theapparatus according to claim 5, wherein the connecting means comprisestwo switches are connected in series between the voltage source and thefirst storage device, the other between the two storage devices.
 8. Theapparatus according to claim 4, wherein the first storage device issubstantially larger than the second storage device.
 9. A power supplyapparatus comprising: a power supply; a voltage regulator; first andsecond capacitors provided between said power supply and said voltageregulator in parallel to said power supply; a first switch providedbetween said power supply and said first capacitor to open or close inresponse to a first control signal; a second switch provided betweensaid power supply and said second capacitor to open or close in responseto a second control signal; and a control circuit which generates saidfirst and second control signals to said first and second switches suchthat said second switch opens and then said first switch closes when avoltage of said second capacitor decreases to a first predeterminedlevel, and such that said first switch opens and said second switchcloses after a first predetermined time period from the closing saidfirst switch.
 10. The power supply apparatus according to claim 9,wherein said first predetermined time is a time period until a voltageof said first capacitor reaches a second predetermined level after saidfirst switch is closed.
 11. The power supply apparatus according toclaim 9, wherein said control circuit generates said first and secondcontrol signals to repeat a switching operation in which said secondswitch opens and then said first switch closes when the voltage of saidsecond capacitor decreases to said first predetermined level, and saidfirst switch opens and said second switch closes after said firstpredetermined time period from the closing said first switch.
 12. Thepower supply apparatus according to claim 9, wherein said controlcircuit monitors the voltage of said second capacitor and generates saidfirst and second control signals based on the monitoring result.
 13. Thepower supply apparatus according to claim 9, wherein said secondcapacitor is larger in capacitance than said first capacitor.
 14. Apower supply apparatus comprising: a power supply; a voltage regulator;first and second capacitors provided between said power supply and saidvoltage regulator in parallel to said power supply; a first switchprovided between said power supply and said first capacitor to open orclose in response to a first control signal; a second switch providedbetween said power supply and said second capacitor to open or close inresponse to a second control signal; and a control circuit whichgenerates said first and second control signals to said first and secondswitches such that said second switch opens and then said first switchcloses when a voltage of said first capacitor decreases to a firstpredetermined level, and such that said first switch opens and saidsecond switch closes after a first predetermined time period from theclosing said first switch.
 15. The power supply apparatus according toclaim 14, wherein said first predetermined time is a time period until avoltage of said first capacitor reaches a second predetermined levelafter said first switch is closed.
 16. The power supply apparatusaccording to claim 14, wherein said control circuit generates said firstand second control signals to repeat a switching operation in which saidsecond switch opens and then said first switch closes when the voltageof said first capacitor decreases to said first predetermined level, andsaid first switch opens and said second switch closes after said firstpredetermined time period from the closing said first switch.
 17. Thepower supply apparatus according to claim 14, wherein said controlcircuit monitors the voltage of said first capacitor and generates saidfirst and second control signals when the voltage of said firstcapacitor decreases to said first predetermined level.
 18. The powersupply apparatus according to claim 14, wherein said second capacitor islarger in capacitance than said first capacitor.
 19. The power supplyapparatus according to claim 14, wherein said control circuit monitorsthe voltage of said first capacitor and an output voltage of saidvoltage regulator and generates said first and second control signalsbased on the voltage of said first capacitor to the output voltage ofsaid voltage regulator.